1. Technical Field
The present invention relates generally to electronic packaging, and more particularly, to an organic semiconductor chip carrier and method of forming the same.
2. Related Art
As the demand grows in the industry for miniaturized high performance semiconductor packages, the need to manufacture a reliable device having high density connections becomes increasingly important. In other words, producing a device having the largest number of chip connections over the smallest possible area is one of the primary objectives. It is also important to produce a structure capable of providing adequate “wireout” capabilities to take advantage of the high density connections.
FIG. 1 shows a cross-sectional view of a related art semiconductor chip carrier 10. The carrier 10 includes a ground plane 12, a first dielectric layer 14 on each side of the ground plane 12, a signal layer 16 over each first dielectric layer 14, a second dielectric layer 18 over each signal layer 16, a power core 20 over each second dielectric layer 18, and a third dielectric layer 22 over each power core 20. The carrier 10 has a plurality of copper plated through holes 24, wherein the copper plating forms a “dogbone” connection pad 28 on the surface of the carrier 10. A redistribution layer 30 covers the surface of the carrier 10. The redistribution layer 30 contains contact areas 34, which facilitate electrical connection of semiconductor chips (not shown), through interconnections (also not shown), to the dogbone connection pads 28 of the plated through holes 24.
FIG. 2 shows a top view of the related art semiconductor chip carrier 10. The dogbone connection pads 28 consume a large portion of the surface area on the carrier 10. This is because the interconnection contact area 34, the area upon which the interconnection is mounted, is offset from the plated through hole 24. As a result, the density of plated through holes 24 and interconnections for each carrier 10 is limited.
Additionally, due to differences in the coefficient of thermal expansion between the chip carrier, the chips and the interconnections therebetween, internal stresses develop within the semiconductor package during thermal cycling, which may eventually lead to device failure.
As a result, there exists a need in the industry for a more reliable, compact semiconductor device.